The present invention relates to an electrically erasable programmable read only memory (EEPROM) device and a method for erasing and programming the same and, more particularly, to an EEPROM capable of being erased and programmed without disturbance of unselected memory cells during an erase or program operation and to a method for erasing and programming therefor.
An EEPROM is a read only memory that can be erased and reprogrammed electrically in circuit. There are various technologies for basic memory elements used in the EEPROM, but the most widely used is based on floating gate transistor having floating gate tunnel oxide (FLOTOX) which was developed from the floating gate transistor of ultra-violet erasing type EPROM. The floating gate transistor of FLOTOX EEPROM is the memory element that may be erased and programmed electrically by employing the tunneling of electrons from a drain to a floating gate and from the floating gate to the drain via the tunnel oxide of about 500.ANG. (see U.S. Pat. No. 4,203,158). However, when the FLOTOX-type transistor is actually used in an EEPROM memory cell array, one EEPROM cell, i.e., one bit cell, of the single FLOTOX-type transistor is not sufficient for the proper function of the memory, but a second transistor called a selection transistor is required. If one selection transistor is not used to each EEPROM cell, high voltage applied to one drain appears on drains of other cells in the same bit line (or column) thereby resulting in erase for the unselected cells. We call this the disturbance of cell. Therefore, the requirement of not only two transistors per bit but also additional tunneling area in floating gate transistors results in too large chip area to be applied for high-density FLOTOX EEPROM devices.
To solve such drawback, a flash EEPROM cell, which may use one transistor per bit and instantaneously erase contents of all memory cells, has been developed. The basic structure of such cell is similar to that of a double polysilicon floating gate transistor of the prior art EPROM. But, the significant difference between the both is that edges of the source or drain region and the floating gate are overlapped via a thin gate oxide. The memory cell array employing the EEPROM cell of such structure is disclosed in U.S. Pat. No. 4,698,787. The memory cell of this patent is erased by Fowler-Nordheim (F-N) tunneling of electrons via the overlapped area from the floating gate to the source region, and is programmed by hot electron injection from a channel region to the floating gate. In the memory cell array of this patent, control gates of cells in the respective rows are connected to the respective corresponding word lines (or X lines), drains of the cells in the respective columns are connected to the respective corresponding bit lines (or Y lines) and sources of the cells are in common connected to a single common source line. In this memory cell array, since the erase operation of cells is achieved by applying high voltages to the common source line and grounding all word lines, there is a limitation that all of the cells in the same chip are erased at a time. Also, since the programming of the cells is achieved by applying high voltages to the drain of the cell in order to generate the hot electrons, it is necessary to flow large drain current. Therefore, a high voltage supply source having a large current capacity is required for programming the cell from the chip outside.
Other prior art of the flash EEPROM is an EEPROM cell having a NAND structure which is disclosed in 1988 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, at pages 33 to 34. Referring to FIG. 1 in connection with the technology disclosed in this paper, it is illustrating an equivalent circuit diagram of a flash EEPROM memory cell array 10 in which a plurality of memory strings MS11 to MS22 connected between each of bit lines (or column lines) BL1 and BL2 and the ground are arrayed in rows and columns. Each of the memory strings (or NAND cells) is that drain-source paths of a string selection transistor ST, memory cells MC1 to MC8 of 8-bits and a ground selection transistor GT are connected in series. A string selection line SSLk, word lines WLk1 to WLk8 and a ground selection line GSLk are respectively connected to gates of selection transistors ST in memory strings MSk1 to MSk1 in the k-th row, control gates of memory cells MC1 to MC8 and the gate of ground selection transistors GT ("k" stands for a positive integer number).
Each of the memory cells MC1 to MC8 has the same structure with each other. The structure is fabricated by the known double polysilicon gate technology equal to that of the above-mentioned flash EEPROM cell. The edge of the floating gate overlaps the edge of the drain with the gate oxide of 100.ANG. interposed therebetween. The floating gate and the control gate are respectively formed by first and second polysilicon layers. The oxide thickness between the floating gate and the control gate is about 250.ANG..
Discussion will be made about erase program and read operations in reference with the disclosure of the paper.
The erase operation of the respective memory cells may be achieved by F-N tunneling of electrons from channels to floating gates. For example, erase of whole memory cells MC1 to MC8 in memory strings MS11 and MS12 in the first row may be achieved by applying 13 volts to word lines WL11 to WL18 and also applying zero volt to all bit lines BL1 and BL2, after turning ON string selection transistors ST and ground selection transistors GT by applying 5 volts to the string selection line SSL1 and the ground selection line GSL1. Therefore, each of memory cells MC1 to MC8 in memory strings MS11 and MS12 is erased to an enhancement transistor having a positive threshold voltage (Vte=0.5 to 2 volts) by absorbing electrons into the floating gate.
On the other hand, program operation may be performed per each selected bit by tunneling of electrons from the floating gate to the drain. For example, for selectively programming a memory cell MC4 in the memory string MS11, after causing to respectively turn on and off the string selection transistor ST and the ground selection transistor GT by respectively applying 20 volts and the ground on the string selection line SSL1 and the ground selection line GSL, there is applied 20 volts on unselected word lines WL11 to WL13 between the selected bit line BL1 and the selected word line WL14 and also applied the ground on the selected word line WL14 and unselected word lines WL15 to WL18. Therefore, high voltages on the bit line BL1 transfer to the drain of the selected memory cell MC4 via unselected memory cells MC1 to MC3 in the memory string MS11, and then electrons in the floating gate flow out into the drain of MC4 via the overlapped region, due to the voltage difference between the drain and the floating gate of MC4. As a result, the memory cell MC4 is programmed into a depletion transistor having a negative threshold voltage (Vtp=-2 to -5 volts).
The read operation of the memory cell MC4 in the memory string MS11 may be achieved by grounding the word line WL14 and applying the power supply voltage Vcc (=5 volts) on the string and ground selection lines SSL1 and GSL1 and the unselected word lines WL11 to WL13 and WL15 to WL18. If the memory cell MC4 has already been programmed, current will flow on the bit line BL1 because of the conduction of the memory cell MC4. However, if the memory cell MC4 were an erased cell, current will not flow on the bit line BL1 by the nonconduction of the memory cell MC4. Therefore, a sense amplifier may read by sensing the current on the bit line BL1.
Since the memory string as mentioned above is connected through one contact hole on the bit line and includes two selection transistors per 8-bits, it may be applied to high-density memory devices. Moreover, since the memory string may be erased and programmed by F-N tunneling of electrons, the current dissipation is very low during its operation. Therefore, it has an advantage of being able to use on-chip high-voltage pulse generator required for erasing and programming employing a single power supply (5 volt power supply).
However, the NAND cell has problems as follows.
The first problem is the disturbance of unselected memory cell arising during the program operation. For example, we will assume that the memory cell MC4 in the memory string MS11 is being programmed. Word lines WL11 to WL13 are applied by the pass voltage (20 volts) higher than the erase voltage (13 volts) required for erase in order to transfer the program voltage (20 volts) applied on the bit line BL1 to the drain of memory cell MC4. Therefore, programmed memory cells on other bit lines connected to word lines WL11 to WL13, i.e., memory cells MC1 to MC3 in the memory string MS12, may be erased automatically. Therefore, it is impossible to erase and program each word line of the memory array and it has a limitation that the program should be sequentially performed from the lowermost cell to the uppermost cell.
The second problem is the over-erase of memory cells, i.e., the increasing of the threshold voltage of erased cells. During the program operation, since the pass voltage (20 volts) even higher than the erase voltage (13 volts) is applied to word lines above the selected word line (hereinbelow referred to as "pass word lines"), for example, word lines WL11 to WL13 where MC4 in the memory string MS11 is selected, the over-erase of memory cells arises at unselected memory cells on the pass word lines. According to repetition of erase and program, even when the high erase voltage are continuously applied to memory cells programmed into erased states, the over-erase arises. Therefore, the existance of any one cell over-erased in a memory string makes slow the reading speed of programmed cell in the memory string or, in the worst case, causes a reading error.
The third problem is the disturbance of cells due to the over-program. During the program operation, since the word line of memory cell coupled just below the selected memory cell is grounded, if the selected memory cell were over-programmed, high program voltage (20 volts) is transferred to the drain of the next memory cell via the drain-source path of the selected memory cell, thereby causing the next memory cell to be programmed undesirably.